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Experimental and theoretical studies of EOS/ESD oxide breakdown in unprotected MOS structures Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1990 p 162 68 66 CDM ESD Sensitivity Testing: Charged Device Model (CDM) Component Level ESD Association Standard, D53, 1997 67 Kitamura Y, Kitamura H, Nakanishi K, Shibuya Y Breakdown of thin gate-oxide by application of nanosecond pulse as ESD test Proceedings of International Test and Failure Analysis (ITSFA), 1989 p 193 9 68 Maloney TJ Designing MOS inputs and outputs to avoid oxide failure in the charged device model Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1988 p 220 27 69 Renninger RG Mechanism of charged device electrostatic discharge Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1991 p 127 43 70 Renninger RG, Jon M-C, Lin DL, Diep T, Welsher TL A eld-induced charged device model simulator Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1989.

Revised Resistance Design (RRD). RRD covers subscriber loops as long as 24 kft. Loop length is broken down into two ranges from 0 ft to 18,000 ft, where the maximum loop resistance is 1300 Q , and from 18,000 ft to 24,000 ft, where the maximum loop resistance is 1500 Q . H88 loading is used on loops longer than 18,000 ft. Two gauge combinations may be employed selected from the following three wire gauges: 22, 24, and 26 gauge.

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p 59 71 71 Fong Y-P, Hu C The effects of high electric eld transients on thin gate oxide MOSFETs Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1987 p 252 7 72 Lin DL ESD sensitivity and VLSI technology trends: thermal breakdown and dielectric breakdown Proceedings of the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, 1993 p 73 82 73 Degraeve R, Pangon N, Kaczer B, Nigam T, Groseneken G, Naem A, et al Temperature acceleration of oxide breakdown and its impact on ultra-thin gate oxide reliability VLSI Technical Symposium, 1999 p 59 60..

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I would like to thank Cathy Ralston of the University of Guelph, in particular, who read every word of the eighth edition manuscript and checked the exercises and problems as well as their solutions in the Instructor s Manual to help ensure their accuracy. Additionally, a number of professors and instructors have given suggestions and advice, which aided in the development of the eighth and previous editions. I thank them for taking the time and effort to share their thoughts with me: Earl R. Arrowood, Bucks County Community College Herbert F. Brown III, University of South Carolina Ronald F. Cox, New Mexico State University Karen Greathouse, Western Illinois University Robert A. McMullin, East Stroudsburg University John W. Mitchell, Sault College Susan Reeves, University of South Carolina John Rousselle, Purdue University Paul Teehan, Trident Technical College Thanks to the copyeditor and proofreader of this edition for their assistance. Finally, the editors at John Wiley & Sons, especially JoAnna Turtletaub, Julie Kerr, and Liz Roles, have been especially helpful in bringing the eighth edition to publication. Martin G. Jagels

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